Memory units, such as electrically programmable read only memory (EPROM) arrays, electrically erasable programmable read only memory (EEPROM) arrays, flash EEPROM (FLASH) arrays, self-timed random access memory (SRAM) arrays, and dynamic random access memory (DRAM) arrays, are formed of arrays of individually accessible storage units, organized into rows of data attached to a "word-line".
The memory array has an associated X or row decoder unit which, when memory cell must be accessed (for reading, writing or programming purposes), receives an address signal indicating the desired memory cell. The X decoder decodes the address signal to select the unique word-line associated with the desired memory cell. For each word line to be activated, the X decoder typically first deselects (i.e. discharges) the previously selected word line and selects the word line to be activated (i.e. charges it).
X decoders can either be clocked or unclocked. U.S. Pat. No. 4,843,261 to Chappell et al. describes one clocked X decoder. An unclocked architecture deselects the previously selected word line while selecting the newly selected word line. A clocked architecture, such as the one shown in FIG. 1 discussed hereinbelow, utilizes less space than an unclocked architecture (and is, therefore, generally more desirable); however, clocked architectures perform the selection and deselection operations in series with each other. Thus, in clocked architectures, the deselection operation must be fully completed before initiating the selection operation.
The time required for deselection or selection depends on the time constant (the "RC" delay) of the word lines. The RC delay is a function of the resistance (R) and capacitance (C) of each word line, both of which are functions of the cross-sectional area and length of each word line. It is noted that, the larger the RC delay is, the longer it takes to discharge or charge the word line.
For low and medium density memory arrays 10, the word lines are of a length such that their RC delay is relatively low. Thus, the time required to deselect and then select, which occurs each time the word line changes, is acceptable. However, for high density memory arrays, the word lines become quite long and, as a result, have an increased RC delay. Every X nanoseconds increased RC delay causes a 2X increased word line access time (comprised of deselection and selection), which can be unacceptably long.
U.S. patent application Ser. No. 08/634,282, entitled "A Row Decoder Having Triple Transistor Word-Line Drivers" and assigned to the common assignees of the present invention, is incorporated herein by reference. The row decoder of U.S. application Ser. No. 08/634,282 is shown in FIG. 1, to which reference is now made.
The row decoder of FIG. 1 includes pre-decoders 10 which receive the addresses to be accessed, dual supply predecoders 12 capable of delivering both conventional voltages Vcc and high voltages Vpp, a plurality of main decoders 14 each associated with isolation elements 15, and a multiplicity of word-line drivers, one per word-line and K per main decoder 14. Each word-line driver includes one p-channel, charging transistor 20 and one discharging transistor 30 on one side of the word line and one n-channel, discharging transistor 22, on the opposite side of the word-line, labeled 24. Each main decoder 14 supplies a control line Fx (where x ranges from 0 to J) to a block of integrated word-line drivers which, in response, control their associated word-lines 24.
The dual-supply predecoders 12 are connected through select lines Ry (where y ranges from 0 to K) to each block of word-line drivers. The select lines Ry carry the voltage (Vcc for reading and Vpp for programming) to be provided to the selected word-line 24.
The discharging transistors 22 are controlled by a row decoder disable line, labeled "DISABLE", which is a clocked signal active during deselection periods. The DISABLE signal is also provided to predecoders 10 for disabling the control lines Fx, and thus the charging transistors 20, during deselection.
Discharging transistors 30 are n-channel transistors controlled by their respective Fx signal. When the DISABLE signal becomes active, it directly activates the discharging transistors 22 on the far end of the word lines 24, it causes the Fx control lines to disable the p-channel charging transistors 20 and to activate the n-channel discharging transistors 30. Thus, each word line 24 is discharged through two discharging transistors, 22 and 30.
The spatial separation of discharging transistors 22 and 30 provides two separate discharge paths for the charge on the relevant word-line. The two separate discharge paths, in effect, divide each word line in two. Thus, for discharging, the RC delay of the word line is that of a word line of half the length. The result is that the two discharging transistors 22 and 30 discharge, by a factor of 4, more effectively than would a single discharging transistor 22 or 30 of almost any size at only one end of the word line.